1. Field of the Invention
The present invention relates to an apparatus and method for saving power in a system using a microprocessor. More particularly, the present invention relates to an apparatus and method for a software-oriented power saving technology for reducing power consumption by saving bit switching power in a system using a microprocessor.
2. Description of the Related Art
The significance of a low power design is continuously increasing as power consumption of mobile equipment increases due to faster data rates and the addition of supplementary functions.
At present, a hardware-oriented low power technology is mostly used at a chip level, but has limitations. A dynamic power in a Complementary Metal-Oxide Semiconductor (CMOS) integrated circuit can be given as Equation 1 below:Pd=α×C×V2×f  (1)
Here, the ‘α’ denotes an activity rate representing an average frequency of transition, which consumes power, implemented by a node during a single clock period. The ‘C’ denotes a capacitive load upon switching. The ‘V’ denotes a supply voltage and the ‘f’ denotes a switching frequency.
In Equation 1, the dynamic power can be reduced through a reduction of the activity rate, the supply voltage, and the switching frequency. Among these, the reduction of the activity rate has a relation to bit switching within a register, and this can be implemented by software.
FIG. 1 is a diagram illustrating a principle of power optimization using a conventional bit switching.
Referring to FIG. 1, in performing any operation, a bit switching operation frequency can be reduced through a change of only a register. If a variation of registers before the change is equal to ‘r1 (0001)→r14 (1110)→+r3 (0011)’, bit switching of 7 bits takes place. However, if a variation of registers after the change is equal to ‘r12 (1100)→r8 (1000)→r0 (0000)’, that is, if r1 changes into r12, r14 changes into r8, and r3 changes into r0, bit switching is reduced to 2 bits.
If this principle is applied to all registers illustrated in FIG. 1, a sum of total bit switching reduces from 20 bits to 6 bits. However, upon a change of a register, it is required to investigate if the register is changeable based on several conditions.
FIG. 2 is a diagram illustrating a conventional bit switching optimization scheme.
There is a disadvantage in that the technology illustrated in FIG. 1 is applied only for a single code and a single function as illustrated in FIG. 2 because, when a register changes, there are the following limitations:
First, a register is changeable only when a register of each function has no influence on a register of other functions, and
Second, a change of a register is limited depending on a compile mode. A register used for a specific purpose is difficult to change.
Thus, there is a demand for a scheme applicable to a global function and a global code by considering and addressing the above limitations.